The present invention relates to formation of vertical devices by electroplating, and more specifically, to formation of vertical structures using electroplating techniques.
Electroplating, which is also referred to as electrodeposition, has been widely used for metallization in semiconductor manufacturing. Electroplating is particularly useful for forming deep metal vias that extend through the inter-level dielectric (ILD) layers to connect the metal contacts in different metal levels.
One of the conventional electroplating methods commonly used for copper metallization in semiconductor manufacturing processes is referred to as the damascene or superfilling method, as disclosed in U.S. Pat. No. 6,709,562 entitled “METHOD OF MAKING ELECTROPLATED INTERCONNECTION STRUCTURES ON INTEGRATED CIRCUIT CHIPS” and illustrated herein by FIGS. 1A-1C. First, a template structure is formed, which comprises a substrate 100 and an inter-level dielectric (ILD) layer 101, as shown in FIG. 1A. The substrate 100 may be formed of either an insulator or a semiconductor with little or practically no conductivity. The ILD layer 101 contains deep vias 102 therein, which can be readily formed by well-known photolithography and etching techniques. Next, a continuous metal seed layer 103 is deposited over the entire template structure, as shown in FIG. 1B. The metal seed layer 103 covers both the top surface of the ILD layer 101 and the sidewalls and bottom surfaces of the deep vias 102. The metal seed layer 103 comprises one or more contacts (not shown), through which an electroplating current can be applied to the metal seed layer 103. Electroplating of the template structure is then carried out by using a special electroplating chemistry, which preferentially deposits metal 104 into the deep vias 102 of the ILD layer 101 (i.e., the metal 104 is deposited into the deep vias 102 at a rate that is significantly faster than on the top surface of the ILD layer 101) to form metal wire structures free of voids, as shown in FIG. 1C.
The above-described superfilling method has advantages in filling vias with a single element or a homogeneous alloy of two or more different element. However, the superfilling method cannot be used to form a column with modulated compositions along a longitudinal axis thereof, due to several reasons. First, the electroplating step in this method proceeds simultaneously on the bottom surface and over the sidewalls of the deep vias 102. Therefore, the superfilling method can only be used to form compositionally homogeneous structures (i.e., structures comprising the same metal or metal alloy throughout the entire structures), but not compositionally modulated structures (i.e., structures comprising alternating layers of different material compositions along the longitudinal direction). Further, the superfilling method requires a special electroplating chemistry, which contains numerous different additives, each of which exerts a different effect on the metal plating rate to jointly achieve the preferential metal deposition. Therefore, the superfilling method has so far only been used for plating of a single metal, such as copper, but not for plating of metal alloys or alternating layers of different metals, due to uncertainties related to how the different additives in the special electroplating chemistry will affect the plating rates of different metals.
Another conventional electroplating method, which is commonly used for forming metal wire structures, is referred to as the plating through mask method and is illustrated by FIGS. 2A-2B. In this method, a continuous metal seed layer 203 is firstly deposited over a surface of the substrate 200, followed by the deposition of an inter-level layer 201 of photo-resist, dielectrics, or doped semiconductors with relatively low conductivity over the metal seed layer 203. Next, deep vias 202 are formed in the inter-level layer 201 by photolithography and etching, as shown in FIG. 2A. During subsequent electroplating, an electroplating current is applied to the metal seed layer 203 to deposit a metal 204 over the bottom surfaces of the deep vias 202 and gradually fill up the deep vias 202 to form vertical metal wire structures, as shown in FIG. 2B.
The plating through mask method is a bottom-up filling process, which can be used for forming not only metal wire structures that comprise a single metal, but also those comprising metal alloys. Further, it can be used to form compositionally modulated structures comprising alternating layers of different material compositions along longitudinal axes of the structures.
However, a major disadvantage of the traditional plating through mask or bottom-up plating process is the requirement for the continuous metal seed layer 203. Because the metal seed layer 203 is continuous over the entire surface of the substrate 200 and connects all the metal wire structures, such metal wires cannot function independently of one another and therefore cannot be used to form separate electronic devices, unless the metal seed layer 203 is selectively removed. However, because the metal seed layer 203 is sandwiched between the inter-level layer 201 and the substrate 200, it is almost impossible to remove it without disrupting or damaging the inter-level layer 201 and the substrate 200.
There is a continuing need for an improved method for forming vertical device structures. More importantly, there is a need for an improved method for forming separate vertical device structures that comprise alloys or alternating layers of different conductive materials.